A little late but maybe I can help you.
The Spoiler Elevator Computer is based on, in total, four CPUs. Two 80186 and two 8086. Airbus computer in general, or at least in case of FBW computer, are based on a redundant architecture. They consist of a command and monitoring channel. As the name implies, the COM channel processes flight control laws and does servo control. The MON channel processes flight control laws, but there is no servo control, instead it monitors the position of the surfaces, namely spoilers plus in case of ELAC fail the THS and elevators.
Now some details:
COM and MON are physically separated in the computer housing. In the center of the LRU are four slots where a PSU modul can be fittet. Two of them are used. One PSU modul for COM and one for MON. The slots separate the COM and MON Boards. COM consists of three boards: Main CPU 80186, Servo CPU 8086 and a Servo/IO board. MON the same but without Servo/IO. The CPU Boards are identical, there is no difference between COM and MON. Software for the Main CPU is stored in an OBRM (128 KByte), Airbus terminology for a ROM Module. When you saw outside pictures of the SEC: the OBRMs are the labeled cartridges. They are directly connected to the Main CPU board. Software for the 8086 is stored on two socketed ROMs (64KByte together) on the board. Servo and Main communicate via a dual port ram. Servo jacks or rather servo valves, related LVDTs and so on are connected via relays located on Servo CPU and Servo I/O. For THS and elevator, COM and MON relays are in series. For spoilers relays are located on Servo IO (if I remember correctly) and controlled by MON. Relays can be controlled by the CPUs or the Engage Logic. The engage logic is a set of PLDs with basic logics implemented, taking over even when all CPUs aren't working. For example, the Main CPU is monitored by a watchdog timer. It has to be periodically resetted, or it will trigger the engage logic, which in turn will switch the relays. I think even the SEC push button on the overhead panel is connected to the engage logic and the small light which will illuminate in case of failure.
Arinc429 output is partly done by the CPUs, they generate four bytes with data and label included by software, and then push it into a PLD byte after byte, which then does parity and parallel to serial conversion plus arinc adaption (RZ Coding).
One transmission PLD is fitted on Main and one on Servo. Main sends data to the FCDC and Servo should process the output to the opossite channel (Arinc429 Cross Talk Bus).
Arinc input is managed by one set of PLDs on the Main CPU board. They validate the data and load it into a dual port ram. Not the same dual port ram as mentioned above for main-servo communication! The "hardware driver" software on Main loads byte after byte from the dual port ram into its own ram and does final depacking. (mostly just a few bit shifts in case of air data and so on and shifts plus masking in case of discrete words where each bit represents a state)
For discrete IO adaption circuits are used (changing voltage levels) and then inputs are multiplexed on the 16th bit of the x86 data bus. Output the same just the other way around.
All servo related hardware is located on the Servo CPU and Servo IO board. LVDT and RVDT signals are demodulated in hardware and then read in by the 8086 via a "diy" integrating ADC.
Analog input from potentiometers like sidestick, thrust lever and speedbrake lever are processed by the 80186. They are multiplexed onto a single ADC.
On the Servo IO board op amps for driving and regulating the current commanded by the 8086 through the servo valves are used. A set of four dual DACs drive the op amps.
Momentary current of each servo output can be read back, also by the 8086, to verify correct operation of the analog servo current control.
Maybe I forgot something but for the beginning, that should by much information. Basically the SEC is "just" a big discrete build MCU, or let's say two MCUs (COM and MON).
Hope I could help...