What's holding equipment manufacturers from going into multicore, RTOS- based equipment?
Recently, Rockwell Collins certified its display systems based on RTOS:
Why are major players not moving into these segments like RTOS, multicore processor? Is it because of certification difficulties?
Development costs, complexity and need.
On a system that has to be hard real time multi-core is a pain(think expensive) and most things that need to be hard real time are not that complex. Things that don't need to be hard real time don't need to be RTOS, so you have one system that handles all the hard real time stuff and one that runs Linux and handles the other stuff.
AFAIK multicore technology is currently used in some automotive solutions, however usually not as SMP (symmetrical multicore processing) but either AMP (asymmetrical multicore processing), where each core runs its own dedicated tasks, or as lock-step dual cores running the same code for extra reliability.
This article by Freescale engineers offers some reasons for it being introduced in cars:
Automotive SoCs have traditionally been single core, since not much computational work or high end applications were targeted on them. Automotives were simpler, so were the applications and so were the SoCs. As more and more electronics made room in the automotives, the complexity of the SoCs kept on increasing. Now the focus is to have most of the automotive under electronic control.
High end automotives produced these days provide features like electronic stability control (ESC), traction control system (TCS), advanced driver assistance systems (ADAS) etc. These features require complex SoCs at heart which can collect, process and transfer data at a fast rate from multiple peripherals.
No matter at how much high frequency the single core is operating on, it will always have performance bottlenecks & challenges while performing multiple tasks. Single core running on higher frequency consumes more power. This makes the single core architecture unfit for ultra low power applications. Dual core based SOC architecture provide better tradeoff in performance and power consumption than single core based architectures.
Freescale also has a document Embedded Multicore: An Introduction expanding on advantages and challenges of multicore chips in embedded environments. For example (on interconnect buses):
Ironically, although microprocessors can perform almost instantly the sorts of complex complications that decades ago institutions spent millions on and built rooms for, the step into multicore processing has brought a simple problem to light: Because the total bandwidth must be divided among the bus masters,more cores means less bandwidth per core.
Also, with increased bus traffic, the risk of collisions increases and this lowers bandwidth even further. In short, a bus does not scale well above four cores.
While automotive industry has its own safety & certification requirements, I think it's somewhat easier for manufacturers to experiment with multicore solutions on ground, compared with planes which have to fly properly in all situations and have much more potential for damage, so multicore adoption will likely be much slower.
However, they may be introduced in avionics too at some point:
The Multicore for Avionics (MCFA) working group, which includes representatives from BAE Systems, BARCO, Boeing, EADS, ELBIT, GE Aviation, Hamilton Sunstrand, Honeywell, Rockwell Collins, Thales, and Freescale, was established to help commercial avionics companies leverage the performance, power, and size advantages of sophisticated embedded multicore processors, such as those from Freescale
Report from the 2013 WG meeting: http://onboard.thalesgroup.com/successful-multi-core-for-avionics-working-group-meeting-with-authorities/
Multi core systems means at the processor level, there has to be an interconnect bus that shares data. This interconnect brings some level of indeterminism at nano-second levels - what if the data requested is in the cache of core 1 and the process is in core 2? What if contention arises?
Also, when RTOS starts the micro-kernel how will it leverage multiple cores - as separate units? Will it meet stringent safety guidelines if it shares L3 cache but has separate L1 / L2 cache?
